1. Field of the Invention
The invention as disclosed in the specification relates to the structure of thin-film transistors (referred to as xe2x80x9cTFTsxe2x80x9d hereinafter in the specification). The invention also relates to a method for manufacturing the same.
2. Description of the Prior Art
Prior known TFTs are manufactured using a silicon thin-film as formed on a glass substrate or quartz substrate.
Most TFTs that are currently practiced and implemented are those which employ a non-crystalline silicon film (amorphous silicon film) as an active layer thereof.
The amorphous silicon film may be relatively easily fabricated by use of plasma chemical vapor deposition (CVD) techniques.
It has been considered that the technological trend of liquid crystal display (LCD) devices of the active matrix type in near future is to further develop the xe2x80x9csystem on panelxe2x80x9d structure, in which several types of circuits are integrated together on a single glass substrate or quartz substrate, which circuits may include active-matrix circuitry and circuitry for driving the same as well as circuits handling both video image information and a variety of kinds of information items.
To attain such structure required, the currently available TFTs using one or more amorphous silicon films are encountered with a problem: the characteristics thereof remain too low.
Those TFTs using such amorphous silicon films remain low in characteristic, which in turn results in limited applicabilityxe2x80x94the TFTs are merely applicable to certain active matrix circuits of the active-matrix LCD devices.
More practically, in the TFTs using amorphous silicon films, the mobility is 1 cm2/Vs or less. Yet further, only N-channel type ones are implementable for practical use; P-channel type ones remain too low in characteristic so that these cannot be reduced to practice.
Note here that the mobility of metal oxide semiconductor (MOS) transistors using single-crystalline silicon wafers is typically greater than or equal to 1000 cm2/Vs.
One approach as partly practiced today to overcome this problem is the use of specific TFTs using a crystalline silicon film.
One method for obtaining the crystalline silicon film is to thermally crystallize an amorphous silicon film upon heat application thereto.
For example, plasma CVD techniques or low-pressure CVD techniques are employable to form an amorphous silicon film, which is then heated at temperatures of 800xc2x0 C. to 1000xc2x0 C. for several hours thus obtaining a crystalline silicon film with polycrystalline state.
This method has been called the xe2x80x9chigh-temperaturexe2x80x9d process due to the fact that high temperatures are utilized which are needed for fabrication of standard integrated circuits (ICs).
A TFT with the resultant crystalline silicon film thus obtained by the aforesaid method is such that an N-channel type one has its mobility of approximately 100 cm2/Vs whereas a P-channel type one has the mobility of 60 cm2/Vs or more or less.
With the characteristics of such degrees, it is possible to form complementary MOS (CMOS) circuits as required to constitute integrated circuits. In addition, it may also be possible to employ such TFTs to configure those circuits that have conventionally been arranged by prior known ICs using single-crystal silicon wafers, although these are not sufficient to fully meet the intended characteristics.
However, in order to fabricate the TFT using the crystalline silicon film, it should be required that a specific substrate with increased thermal resistivity (this is limited to quartz only in the current situation) be employed, which would result in an increase in production cost (due to the cost penalty of such quartz substrate).
An alternative approach as currently studied is to make use of a glass substrate of low cost while adequately rearranging the crystallization method per se. This approach is called the xe2x80x9clow-temperaturexe2x80x9d process due to the fact that fabrication is done through specific processes which require thermal processing at selected temperatures that give no affection to the heat durability of a glass substrate used.
One typical approach incorporating the above concept is a technique for crystallization of an amorphous silicon film at a heat-up temperature that is carefully controlled permitting the glass substrate to thermally withstand.
By way of example, an amorphous silicon film is formed on a glass substrate; then, the resulting structure is heated up at a temperature of 600xc2x0 C. for 48 hours to thereby obtain a crystalline silicon film.
Unfortunately, a TFT employing such resultant crystalline silicon film will fail to exhibit any satisfactory characteristics.
Another problem is that production costs are not so lower than expected because of an increase in heat-up time duration.
Still another approach to the low-temperature process is a technique for irradiation of laser light to thereby alter or transform in nature an amorphous silicon film into the intended crystalline silicon film.
This approach is advantageous in that a glass substrate used remains almost free from heat application.
It is possible for those TFTs obtainable by this technique (called the xe2x80x9claser processxe2x80x9d) to attain superior characteristics which may correspond to the characteristics of TFTs as obtained by high-temperature processes.
It has been found that the TFTs as obtained by the prescribed low-temperature process yet remain too low in characteristic to achieve the system-on-panel architecture required.
The technologies required here may include:
(1) Low-temperature process; and
(2) Attainability of even higher characteristics than those of TFTs obtained by laser processes.
As the technique for satisfying the requirement items, the applicants of this patent application has developed one specific scheme of crystallization which introduces a minute amount of metal element of an amorphous silicon film for later effectuation of thermal processing to thereby perform crystallization. This technique has been disclosed in Published Unexamined Japanese Patent Application No. 7-321337.
Those TFTs employing such crystalline silicon films obtained by this method offer considerably high performance. However, some of the crystalline silicon films obtained by this method can contain therein residual metal elements as have been used for crystallization processes, which residual elements can badly affect the-characteristics of the TFTs.
Practically, with regard to the items of the reliability and the uniformity of characteristics among device, it has been affirmed that the TFTs remain less as compared to the conventional TFTs of low characteristics.
A Study by the present inventors has revealed the fact that the low reliability of device characteristics and low uniformity of characteristics thereof are originated from affection of such metal elements that continue residing within crystalline silicon films fabricated.
An object of the invention as will be disclosed in the specification is to provide a technique adaptable for use with TFTs fabricated using a crystalline silicon film as crystallized using a chosen metal element, for suppression of any possible affection or bad influence of residual metal elements on the TFT device characteristics.
One of the inventive concepts as disclosed in this specification has a high-resistivity region disposed in close proximity to a channel region, and a source or drain region disposed adjacent to said high-resistivity region, featured in that said source or drain region contains therein a metal element for acceleration of crystallization of silicon at a high concentration, and that said high-resistivity region contains said metal element at a low concentration.
A structure of another invention has a high-resistivity region disposed neighboring to a channel region, and a source or drain region disposed neighboring to said high-resistivity region, characterized in that said source or drain region contains therein a metal element for acceleration of crystallization of silicon at a concentration greater than or equal to 1xc3x971019 atoms/cm3, and that said metal element is contained in said channel region and said high-resistivity region at a concentration less than or equal to 1xc3x971017 atoms/cm3.
No particular problems will arise even when the source or drain region contains the metal element at a concentration greater than or equal to 1xc3x971019 atoms/cm3. However, in the high-resistivity region (an offset region or lightly-doped impurity region as will be described in the specification), it is a key feature that the concentration of the metal element is less than or equal to 1xc3x971017 atoms/cm3. This can be said because the presence of such metal element in the high-resistivity region greatly contributes to formation of an unnecessary energy level(s). In addition, it may be permissible that the concentration of metal element in the source and drain regions is greater than the density of defects in said region. In the high-resistivity region, however, it is required that the concentration of the metal element be less than the defect density of the region.
A structure of still another invention is such that the source or drain region is doped with phosphorus therein, and that the.phosphorus doped is higher in concentration than the metal element. With such an arrangement, it becomes possible to obtain extra-high nickel-element xe2x80x9cgetteringxe2x80x9d effect in the source or drain region.
A structure of yet another invention is featured in that the source or drain region is of P type conductivity, and that the source and drain regions are doped with phosphorus.
It may be most preferable in viewpoints of reproducibility and effect that nickel (Ni) is used as the metal element for acceleration of crystallization of silicon.
Additionally, the metal element used may be one or several elements as selected from the group consisting of Fe, Co, Ni, Ru, Rh, Pd, Os, Ir, Pt, Cu and Au.
In the structure with high-resistivity regions such as a lightly-doped impurity region and an offset region being disposed in contact with a neighboring channel region, letting the source and drain regions (at least one of them) be the gettering cites causes the nickel density or concentration to decrease in the high-resistivity regions.
In order to let the source/drain regions be such gettering cites, dope phosphorus into these regions while forcing phosphorus to perform what is called the xe2x80x9cgetteringxe2x80x9d of the metal element. This gettering effect becomes significant in particular when nickel is chosen as the metal element.
The presence of a metal element for acceleration of crystallization of silicon which may typically be nickel will be problematic in those regions which follow:
(1) channel region; and
(2) interface between the channel region and its neighboring region as well as xe2x80x9cnearbyxe2x80x9d regions thereof.
The presence of the aforesaid metal element in the channel region deteriorates an inherent function of the channel that the surface on the side of a gate insulation film can change in conductivity type due to application of an electric field from a gate electrode to form the so called the inversion layer therein.
This takes place because of the fact that if the metal element exists then an increased number of unnecessary energy levels occur in the forbidden band within the channel region.
Typically, a junction of those regions having the opposite conductivity types is formed at the interface between the channel region and its nearby region adjacent thereto, which junction may be an IN junction or PN junction section.
One example is that in one typical TFT structure, its source/drain regions are disposed in contact with a channel region neighboring thereto. In this structure a PN junction is formed at the interface between the channel region and the source/drain regions while the TFT is turned off during operation.
Another example is that in a structure with a lightly-doped impurity regionxe2x80x94typically, a lightly-doped drain (LDD) regionxe2x80x94being disposed at a location neighboring to the channel region, a similar PN junction will be formed at the interface between the channel region and the lightly-doped impurity region during a turn-off operation.
A further example is that in a structure with an offset region placed neighboring to the channel region, a PI or NI junction will be formed at the interface between the channel region and the offset region during the turn-off operation also.
Generally, if the metal element is present at such junction portion or portions of the opposite conductivity types, then these portions reduce their expected effect and functions obtainable from inherent semiconductor junctions. This is due to the fact that the presence of such residual metal element badly behaves to form or create multiple energy levels in the forbidden band.
By way of example, one or more unnecessary energy levels are formed in the junction portions of opposite conductivity types due to presence of the metal element, which results in occurrence of undesired movement or propagation of carriers therethrough.
This in turn causes a decrease in breakdown voltage and an increase in leak current. In addition, since the state does not occur stably, problems arise such as a decrease in reliability and also deviation of characteristics among devices manufactured.
When employing the inventive concepts as disclosed in the specification, it is first possible to significantly reduce the concentration of such metal element in the channel region per se. It is also possible to noticeably reduce the concentration of the metal element in more than one high-resistivity region neighboring to the channel region. Our experimentation reveals that the concentration could have been lowered to a level of 1xc3x971016 atoms/cm3 which is no longer detectable by the secondary ion mass spectrometer (SIMS). Note also that when the concentration of metal element in the high-resistivity region drops down at 1xc3x971017 atoms/cm3 or less, certain technical advantages may be obtainable.
FIGS. 12A and 12B are for explanation of a relative distribution of Ni concentration at respective locations of the active layer of a TFT as obtained by utilizing the invention. FIG. 12A shows schematically the structure of the TFT whereas FIG. 12B illustrates a relative concentration distribution at respective portions. In FIG. 12A, reference numeral 1201 designates a source, 1202 denotes a drain, 1203 indicates a channel, 1204 shows an HRD. In FIG. 12B the transverse axis represents the position whereas vertical axis indicates the relative concentration of Ni.
Arrows shown in FIG. 12B are for indication of the direction of a change of Ni concentration during gettering processes (i.e. whether the concentration becomes higher or lower). The length of each arrow is to indicate a relative magnitude of the ratio of such concentration change.
The term xe2x80x9cHRDxe2x80x9d as used herein refers to high-resistivity region or domain, which may correspond to a lightly-doped impurity region in embodiments to be described later.
Utilizing the invention disclosed in the specification as shown in FIG. 12 may allow reduction of the concentration of a metal element in the high-resistivity region including a lightly-doped impurity region and an offset region, thereby greatly reducing the concentration of the metal element at those parts whereat a certain junction of opposite conductivity types will be formed.
And, it becomes possible to avoid the problem of introduction of the cause for a decrease in breakdown voltage and an increase in leak current while at the same time avoiding problems as to a decrease in reliability and a variation or deviation of characteristics among devices manufactured.
These and other objects, features and advantages of the invention will be apparent from the following more particular description of preferred embodiments of the invention, as illustrated in the accompanying drawings.